1. Field of the Invention
This invention relates to isolation junctions for semiconductor devices.
2. Background of the Invention
Integrated circuits and related semiconductor devices depend on electrical isolation of one component from another. The most common isolation technique for devices made in the same semiconductor wafer is a diffused region of conductivity type which is opposite to that of the bulk of the device. This results in back-to-back P-N junctions interposed between the devices. This process is usually accomplished by solid state diffusion of selected impurities in a pattern between the devices requiring isolation. The diffused isolation regions are tapered with the widest portion being at the surface through which the diffusion operation is performed. Consequently, the available surface area for component manufacture is reduced in size. Additionally, the diffused regions do not have a constant resistivity throughout the diffused region and the resulting P-N junctions formed thereby are not always a step junction. Occasionally, deep electrical isolation junctions require diffusion of impurities through opposed surfaces of the device. This requires extra process steps. In any instance, however, junction isolation of such devices requires high temperatures and extended furnace times such, for example, as 1250.degree. C for 3 days. High carrier lifetime and crystalline perfection of substrate material are degraded in spite of extensive efforts made to preserve them. Sideways diffusion during formation of the isolation junctions wastes a large volume of the substrate which could be used for device fabrication.
Other electrical isolation techniques involves selective etching of the substrate material of the device and growing or depositing silicon oxide in the etched portion of the substrate.
An object of this invention is to provide a new and improved junction isolation means in semiconductor devices which overcome the deficiencies of the prior art.
Another object of this invention is to provide a new and improved junction isolation means in a semiconductor device which optimizes the volume of substrate material available for device and circuit fabrication.
Another object of this invention is to provide a new and improved junction isolation means in a semiconductor device wherein the isolation region is substantially uniform in thickness and resistivity throughout the region.
A further object of this invention is to provide a new and improved junction isolation means in a semiconductor device wherein post diffusion of the P-N junction is practiced to alter the step junction to a graded junction.
In accordance with the teachings of this invention there is provided a semiconductor device comprising a body of semiconductor material having a selected resistivity, a first type conductivity, two major opposed surfaces forming the top and bottom surfaces of the body and a peripheral side surface. At least one region of second and opposite type conductivity is disposed in the body and extends between, and terminates in, the top and bottom surfaces of the body. The material of at least one region of second type conductivity is recrystallized semiconductor material of the body and has a dopant impurity therein, the concentration of which is sufficient to impart the second type conductivity. The recrystallized material has solid solubility of the impurity contained therein. At least one region divides the body into at least two regions of first type conductivity which are electrically isolated from each other. Each region of first type conductivity has top and bottom surfaces which are coextensive with the respective top and bottom surfaces of the body. A P-N junction is formed by the contiguous surfaces of each pair of regions of opposite type conductivity and is an isolation junction for the body. The P-N junction, formed as the result of the thermal gradient zone melting process is a step junction. In particular, the thermal migration of aluminum "wires" through a body of N-type silicon will produce the desired structure.
A configuration which is preferred for isolation means between semiconductor memory arrays and for the manufacture of individual chips embodies two groups of planar regions of second type conductivity in a body of material of a first type conductivity. The arrangement of the two groups is such as to present an egg crate configuration in the body.
A post thermal gradient zone melting heat treatment is practiced on the step junction to provide a graded P-N junction as required.
As required, electrical passivating material is disposed on selective surface areas of the body and exposed P-N junctions contained therein.